PLC Problem

[Ken9876]

From diagram, rung 2 is after rung 1 but rung 2 controls rung 1, the one shot is only on for one program scan.. All the inputs will be working, but sometimes rung 1 will not go true. I think the problem is the scan time and location of the rungs to eachother. Does anyone have some feed back?





1----|--[bit 2]--|----[input 2]---------------------------------------[bit 3]-------
----|--[bit 3]--|

tried to make a pic bit 3 latches the above rung

2-----[input 3]---[ons]------------------------------------------------[bit 2]--------

 

[mcclary's electrical]

From diagram, rung 2 is after rung 1 but rung 2 controls rung 1, the one shot is only on for one program scan.. All the inputs will be working, but sometimes rung 1 will not go true. I think the problem is the scan time and location of the rungs to eachother. Does anyone have some feed back?





1----|--[bit 2]--|----[input 2]---------------------------------------[bit 3]-------
----|--[bit 3]--|

tried to make a pic bit 3 latches the above rung

2-----[input 3]---[ons]------------------------------------------------[bit 2]--------

Is this Rockwell software? Rs logix?

 

[S'mise]

I agree this is a scan problem. Answer depends on the plc type. Some have scan priorities like pre, master, task,...

Move rung 2 higher in the program so its examened before rung 1
Also make sure no calls for srs are below it

or use a set-up rung instead of the ons

 

[ptonsparky]

What type of input is Input 2? It may not be operating within the one scan. I agree, move rung 2 up.

 

[StephenSDH]

This isn't your problem. Because of the 1shot, bit3 will stay true for a scan starting at rung 2 and ending at rung 2. So rung 1 will always see bit3 as true, but it will have to wait until all the other logic executes before it starts at the top rung1 again. It would be better programming to swap rung 2 with rung 1 to keep a logical flow. Possibly input 2 isn't allowing rung 1 to latch.

 

[Ken9876]

This isn't your problem. Because of the 1shot, bit3 will stay true for a scan starting at rung 2 and ending at rung 2. So rung 1 will always see bit3 as true, but it will have to wait until all the other logic executes before it starts at the top rung1 again. It would be better programming to swap rung 2 with rung 1 to keep a logical flow. Possibly input 2 isn't allowing rung 1 to latch.

That's what I think is happening, because input 2 and 3 are from control relay contacts then feed to input cards.


This is a PLC-5 system and RS logix software

 

[StephenSDH]

Before a PLC5 & 500 scan the logic they refresh the input mapping. Because you have real world inputs contacts bounce and/or one of them will beat the other. When the inputs are refreshed occasionally only one of the two inputs are turned on. You can put a timer on your bit 2 to hold it on for several scans, to insure input 2 had time to turn on.

 

[StephenSDH]

Before a PLC5 & 500 scan the logic they refresh the input mapping. Because you have real world inputs contacts bounce and/or one of them will beat the other. When the inputs are refreshed occasionally only one of the two inputs are turned on. You can put a timer on your bit 2 to hold it on for several scans, to insure input 2 had time to turn on.

 

[Controls]

I am not sure exactly how your system works and what you are controlling but,can you do this? :
1-Input 3 comes on and with a one-shot, latch Bit 2.( you may be doing this already, can't tell if Bit 2 is a latch bit)
2-Bit 2 is on and input 2 turns on , this time you latch Bit 3.( You already have it there, not sure if Bit 3 is a latch bit).
3-Add Bit 2 unlatch coil in parallel with Bit 3's coil.

 

[pfalcon]

From diagram, rung 2 is after rung 1 but rung 2 controls rung 1, the one shot is only on for one program scan.. All the inputs will be working, but sometimes rung 1 will not go true. I think the problem is the scan time and location of the rungs to eachother. Does anyone have some feed back?

1----|--[bit 2]--|----[input 2]---------------------------------------[bit 3]-------
----|--[bit 3]--|

tried to make a pic bit 3 latches the above rung

2-----[input 3]---[ons]------------------------------------------------[bit 2]--------

BST XIC B/2 NXB XIC B/3 BND XIC I/2 OTE B/3 << Standard Seal-in Code
XIC I/3 ONS X/X OTE B/2

You are describing a logical relay race as some others have tried to confirm.
In RSLogix under TOOLS.HISTOGRAM you can test the race condition.
When it fails you will see that I/2 is actually OFF when I/3 fires.
When Input 2 later turns ON the ONS will be blocking.

Changing the rung order may not fix your issue.
The program is expecting I/2 to be on when I/3 fires.
If they fire in the wrong order then the logic fails.

For a better analysis I would require a copy of the code with comments. Send me a PM if you are interested.

 

[Ken9876]

Thank You for all the info and help. I'm going to bring this to the attention of our engineering dept. however they aren't very helpful and they don't write the progams in the first place.

 

[ptonsparky]

and here I thought this was just a test, not real life.

 

[VoltzElectric]

Not sure what you are trying to control with the inputs, or what you are looking for, but one suggestion would be to put a XIO (bit 3) in place of your oneshot then it would stay on until your bit 3 came on..........once again, not sure what your logic is controlling.